As the feature sizes of metal-insulator-semiconductor (MIS) devices continue to shrink, the die-to-die and within-die variations in device parameters are continuously increasing. Process variations are particularly critical in semiconductor memory devices, where minimum geometry transistors are commonly utilized in order to conform to rigorous area constraints. Such process variations may impact both stability and leakage in the memory devices. For example, the static noise margin (SNM) of a static random access memory (SRAM) cell quantifies how much voltage noise is required at the cell's internal nodes to flip the cell's logic state. Previous results suggest that there may be almost a 30% variation in SNM with only a 10% variation in the threshold voltages and channel lengths of the transistors forming the SRAM.
“Power gating” is a technique for addressing the leakage of SRAM cells. In a conventional six-transistor (6T) MIS-based SRAM memory cell, the source terminals of the two n-type field effect transistors that form a portion of the cell's two cross-coupled inverters are usually fixed at ground potential (or VSS). When applying power gating to VSS, in contrast, this source voltage is instead varied based on the active/inactive state of the cell. More particularly, with power gating, the source voltage is raised to a “virtual ground” voltage above VSS while the SRAM memory cell is in standby mode, and returned to VSS during read and write operations. Varying the source voltage in this manner has been shown to decrease the leakage of the memory cell, but to also decrease its SNM. Accordingly, the optimum source voltage for the SRAM cell in standby mode may simply be the highest value that is allowed by the SNM.